The model

TODO picture

The capacitor is charged through the resistor with input voltage $U_0$ and it switches when its gate voltage reaches at least $U_s$. We must make all this in the time period $T$.

Charging capacitor

\[ u_c = U_0 \left(1 - \exp \left(-\frac{t}{RC}\right)\right) \tag{1} \]

and since it’s in series other voltages are \[ u_c + u_r = U_0 \]

The energy is conserved in a capacitor but it is dissipated on the charging resistor, it is $E = \int_0^T P \d t = \int_0^T R i_r^2 \d t$. It will be more useful to calculate the dissipated energy in terms of the capacitor voltage so let’s use substitutions based on equation (1). \[ \begin{align} t &= -RC \log\left(1 - \frac{u_c}{U_0}\right)\cr \frac{\d t}{\d u_c} &= \frac{RC}{U_0 - u_c} \end{align} \]

Using Ohm’s law we rewrite $R i_r^2 = \frac{u_r^2}{R}$ and we get the integral \[ \begin{align} E =& \int_{U_B}^{U_T} \frac{(U_0 - u_c)^2}{R}\frac{RC}{U_0 - u_c} \d u_c =\cr =&\int_{U_B}^{U_T} (U_0 - u_c) C \d u_c = C \left[ U_0 u_c - \frac{u_c^2}{2}\right]_{U_B}^{U_T}\cr =& C\left(\left(U_T - U_B\right)\left(U_0 - \frac{U_T+U_B}{2}\right)\right). \tag{2} \end{align} \]

If we plug in the extreme case of $U_B = “0 V”, U_T=U_0$ we get $E=\frac{1}{2} C U_0^2$. In other words the same energy that was stored in the capacitor must have been dissipated on the charging resistor regardless of its resistance.

How long does this all take? The equation (1) (in the form of the integral substitution) comes for the help again. \[ \begin{align} T &= t(U_T) - t(U_B) \cr &= -RC \left(\log\left(1-\frac{U_T}{U_0}\right)-\log\left(1-\frac{U_B}{U_0}\right)\right)\cr &= RC \log\frac{U_0 - U_B}{U_0 - U_T} \tag{3} \end{align} \]

In terms of semiconductor

We work with a semiconductor component whose switching voltage is $U_s$ and noise margin is $\delta U$. Thus we get $U_B = U_s - \delta U, U_T = U_s + \delta U$.

The energy lost (per (2)) in one cycle is $E = 2C\delta U \Delta U$ where $\Delta U = U_0 - U_s$.

The time (3) we need for one cycle is \[ \begin{align} T &= RC \log\frac{\Delta U + \delta U}{\Delta U - \delta U} = RC \log\left(1 + \frac{2\delta U}{\Delta U - \delta U}\right) \cr &\approx RC \left(\frac{2\delta U}{\Delta U - \delta U}\right) \end{align} \] (we assumed $\delta U \ll \Delta U$ for the linear approximation).

Putting it all together

\[ \begin{align} f = 1/T &= RC \left(\frac{\Delta U - \delta U}{2\delta U}\right)\cr \Delta U &= \delta U + \frac{2\delta U}{RC} f \end{align} \]

\[ \begin{align} P &= Ef = 2C\delta U \Delta U f\cr &= 2C\delta U \left( \delta U + \frac{2\delta U}{RC} f \right) f\cr &= \frac{2\delta U^2}{R}\left(RC + 2f\right) f \end{align} \] where $C$ and $R$ are fixed properties of the silicon layout and $\delta U$ is the voltage tolerance around switching point, which is to some extent hard-wired in the silicon too.

Completeness

  • this models only a single switching transistor
  • in reality it is in parallel (e.g. bus width) so the power is multiplied by width
  • in reality it is in series (composed logical circuit) so the time period is divided by depth
  • in reality there is a constant term (various leaks, proportional to memory capacity?)

Corectness

  • discharging the capacitor (presumably a numeric factor only)
  • assumed $\delta U \ll \Delta U$
  • neglected inductance (and loss by radiation)
  • drain through gate (constant term wrt frequency)
  • the capacitor may work in greater range than $(U_s - \delta U, U_s + \delta U)$ (this is likely the hidden devil)